Implementing Hardware Extensions for Multicore RISC-V GPUs

Introduction

In this work, we present a generalized methodology for implementing hardware extensions for multi-core RISC-V-based GPUs. Our generalized solution addresses both the ISA and microarchitecture changes.

Figure 1 illustrates an overview of a standard GPU pipeline with custom fixed-function units A, B, and C (see yellow blocks).

Background

Reference

• Implementing Hardware Extensions for Multicore RISC-V GPUs